1. Field of the Invention
The present invention relates to antifuse technology and to methods for fabricating antifuse elements. More particularly, the present invention relates to methods for fabricating antifuses which minimize the damage to antifuse films during the etch steps performed to form antifuse vias or antifuse contact vias.
2. The Prior Art
Antifuse fabrication processes universally employ an etching step which is used to form an antifuse via in an inter-electrode dielectric layer :which separates the upper and lower antifuse electrodes. During this etching step, it is important to protect the underlying layer of material whether it be an already-formed antifuse material (such as amorphous silicon, silicon dioxide or silicon nitride or some combination thereof) or the upper surface of the upper or lower antifuse electrode (comprising a material such as TiW, Ti, TiN, TiW:N or some other effective metallic barrier film). Where an amorphous silicon antifuse material is employed it is important to maintain the integrity of the barrier layer protecting the amorphous silicon antifuse layer from metal diffusion. A certain barrier metal thickness must be maintained in order to prevent diffusion of atoms from the electrodes into the amorphous silicon. Such contamination degrades the performance of the amorphous silicon dielectric. It is also important to maintain the as-deposited thickness of the amorphous silicon in order to maintain control of the voltage at which the antifuse material will rupture.
In some antifuse structures, the lower antifuse electrode comprises a first metal interconnect layer and the upper electrode of the antifuse comprises a barrier layer to which electrical connection is made through an antifuse contact via etched through a dielectric layer underlying a second metal interconnect layer. In such embodiments, the upper electrode/barrier layer protects the underlying antifuse material from diffusion of atoms from the second metal interconnect layer. It is important to maintain the integrity of this upper electrode/barrier layer to protect the underlying amorphous silicon antifuse layer from metal diffusion.
When either an antifuse via or an antifuse contact via is etched through a traditional continuous dielectric film, such as PECVD oxide, either the antifuse material or the barrier layer over the lower electrode is exposed to the etch during the final over-etch portion of the etch step. Since a typical over-etch is specified at from about 30-60% of the etch time, the exposure of the antifuse material or the barrier layer during the over-etch process will damage these layers. The typical via depth through an intermetal dielectric layer is between about 0.5-1.0 microns deep, and the antifuse material or lower electrode barrier layer is relatively thin, i.e., between about 0.1 to 0.3 microns. Both the antifuse material layer and the barrier layer are sensitive to the loss of 100 angstroms of material. It is thus important to find a way to minimize the amount of via overetch to which these films are exposed.